problem while using `ifdef`elsif`else How to implement OR operation using defines?I have to build a circuit of an arithmetic right shift operator in verilog and include it in a verilog code of a simple computer I've written the code of the circuit with a module and it compiles The inputs to the multiplexer are the module_output_wire and something_else, the select signal is some_condition, = ifdef_directive ifndef`endif `define D00 `define D01 `ifdef D00 reg t00;
Catherine Verilog Doesn T Provide An Equivalent Of C S If Because This Could Result In Bugs Or Something Also Verilog Allows Macro Expansions To Define New Macros
